Metal-oxide-semiconductor field effect transistor (MOSFET) technology is a dominant electronic device technology in use today. Performance enhancement between generations of devices is generally achieved by reducing an overall size of the device, resulting in an enhancement in device speed. This size reduction is generally referred to as device scaling. As MOSFETs are scaled to channel lengths below about 100 nm, conventional MOSFETs suffer from several problems. In particular, interactions between the source and drain of the MOSFET degrade an ability of the gate to control whether the device is on or off. The degradation in control ability phenomenon is called a short-channel effect (SCE). Silicon-on-insulator (SOI) MOSFETs are formed with an insulator (usually, but not limited to, silicon dioxide or sapphire) below an active region of the device, unlike conventional bulk MOSFETs, which are formed directly on silicon substrates, and hence have silicon below all active regions. SOI is generally considered advantageous as it reduces unwanted coupling between the source and the drain of the MOSFET through the region below the channel. Other techniques, such as separation by implantation of oxygen (SIMOX) functions similarly to SOI. The reduction in coupling in SOI and SIMOX is often achieved by ensuring that all the silicon in the MOSFET channel region can be either inverted or depleted by the gate (called a fully depleted MOSFET). As device size is scaled, however, ensuring a fully depleted channel region becomes increasingly difficult, since the distance between the source and drain is reduced. The reduced distance results in an increased interaction with the channel thus reducing gate control and increasing short channel effects.
A double-gate MOSFET structure places a second gate in the device, such that there is a gate on either side of the channel. The double- gate allows gate control of the channel from both sides, reducing SCE. Additionally, when the device is turned on using both gates, two conduction (i.e., inversion) layers are formed, allowing for better channel control. An extension of the double-gate concept is a surround-gate or wraparound-gate concept, where the gate is placed such that it completely or almost-completely surrounds the channel, providing improved gate control. These surround-gate and wraparound-gate concepts are also formed on SOI or SIMOX and are referred to as FinFET devices due to the silicon-etched fin produced above the oxide/insulator level.
Such a FinFET device is presented in U.S. Pat. No. 6,413,802, entitled “FinFET Transistor Structures Having a Double Gate Channel Extending Vertically from a Substrate and Methods of Manufacture,” issued to Hu et al. FIG. 1 illustrates a FinFET transistor 100 in accordance with Hu et al. The FinFET transistor 100 is fabricated on an insulative layer 101 (e.g., SIMOX) and includes a silicon drain island 103 and a silicon source island 105 connected by a silicon fin or channel 107. The drain island 10, source island 105, and channel 107 are each covered by a dielectric layer 109, and a gate 111 extends across the channel 107 and is isolated from the channel 107 by a gate oxide (not shown explicitly) and the dielectric layer 109. Inversion layers are formed on either side of the channel 107. However, the FinFET transistor 100 still relies on photolithography for minimum feature sizes (e.g., a width of the channel 107 and the gate 111).
There is a need in the integrated circuit art for obtaining increasingly smaller devices without sacrificing device performance. The small device size requires small device regions, precise and accurate alignment between regions, and minimization of parasitic resistances and capacitances. Device size can be reduced by putting more reliance on fine line lithography, but as discussed below, it becomes impractical or impossible to continue to reduce feature size and achieve the required greater increase in alignment accuracy. As lithography is pushed to a limit, yield and production throughput decrease.
Four governing performance parameters of a photolithographic system are limit-of-resolution, Lr, level-to-level alignment accuracy, depth-of-focus, and throughput. For purposes of this discussion, limit-of-resolution, level-to-level alignment, and depth-of-focus are physically constrained parameters.
Typical photolithographic techniques are limited by physical constraints of a photolithographic system involving actinic radiation wavelength, λ, and geometrical configurations of projection system optics. According to Rayleigh's criterion,
      L    r    =            0.61      ⁢      λ        NA  where NA is the numerical aperture of the optical system and is defined as NA =n sin α, where n is the index of refraction of a medium which the radiation traverses (usually air for this application, so n≅1) and α is a half-angle of the divergence of the actinic radiation. For example, using deep ultraviolet illumination (DUV) with λ=193 nm, and NA=0.7, the lower limit of resolution is 168 nanometers (1680 Å). Techniques such as phase-shifted masks can extend this limit downward, but photomasks required in this technique are extremely expensive. This expense becomes greatly compounded with a realization that an advanced semiconductor process may employ more than 25 photomasks.
Along with the limit-of-resolution, the second parameter, level-to-level alignment accuracy becomes more critical as feature sizes on photomasks decrease and a number of total photomasks increases. For example, if photomask alignment by itself causes a reduction in device yield to 95% per layer, then 25 layers of photomask translates to a total device yield of 0.9525=0.28 or 28% yield (assuming independent errors). Therefore, a more complicated mask, such a phase-shifted mask is not only more expensive but device yield can suffer dramatically.
Further, although the numerical aperture of the photolithographic system may be increased to lower the limit-of-resolution, the third parameter, depth-of-focus, will suffer as a result. Depth-of-focus is inversely proportional to NA2. Therefore, as NA increases, limit-of-resolution decreases but depth-of-focus decreases more rapidly. The reduced depth-of-focus makes accurate focusing more difficult especially on non-planar features such as “Manhattan Geometries” becoming increasingly popular in advanced semiconductor devices.
Therefore, what is needed is a method of forming a FinFET device with minimum design geometries substantially smaller than achievable with photolithography. Further, the FinFET device must be fabricated by a process that is reproducible and fully adaptable to high-volume semiconductor fabrication processes.